1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit fabrication. In particular, the present invention relates to a bonding pad structure for an integrated circuit, which can enhance peeling resistance ability via mechanical interlocking.
2. Description of the Prior Art
Wedge bonding technologies play a critical role in the fabrication of chip-on-board (COB) circuitry, and have been widely applied to commercial electronic products. With the ongoing progress made by the semiconductor IC fabrication community in the miniaturization of the size of device feature, bonding pads provided for external connections, for example, have been gradually decreased from a layout area of greater than 100 .mu.m.times.100 .mu.m used previously.
Referring to FIG. 1, a conventional bonding pad for an integrated circuit after being bonded is schematically illustrated in a top view. Moreover, FIG. 2 is the cross sectional view of FIG. 1. The bonding pad shown in FIGS. 1 and 2 is formed on a semiconductor substrate 10, in which lots of electronic devices (not shown in the drawing) have been fabricated. For isolation between a subsequently-formed conducting pad 12 and the devices fabricated in the semiconductor substrate 10, an insulating layer 11 is formed to overlie the semiconductor substrate 10. The conducting pad 12 is thereafter deposited on the insulating layer 11. The insulating layer 11 is further in charge of planarization, the thickness of which should be sufficient and which is usually made of borophosphosilicate glass (BPSG). The conducting pad 12 is preferably a metal layer made of multi-layer material of TiN/Al--Si--Cu/TiN/Ti, and serves the function of transmitting an input signal or an output signal, or tying to a power level or a ground level, etc. Reference numeral 13 designates a passivation layer overlying the semiconductor substrate 10 to prevent scratches or cracking in the internal circuitry. The passivation layer 13 is partially etched away to expose a portion of the conducting pad 12 for wedge bonding. Accordingly, the overhang region between the conducting pad 12 and the passivation layer 13 is referred to numeral 14 in the drawing.
Usually, while the bonding procedure is being performed, one end of a conducting line 15 will first be bonded to the exposed portion of the conducting pad 12 by a wedge bonder. However, another end will be drawn in a direction 18 as shown in FIG. 1 and tied to one bond finger of a lead frame (not shown in the drawing) so as to electrically connect the bonding pad to the associated bond finger.
Nonetheless, although the semiconductor industry has made progress on miniaturization, the wedge bonder used for the chip-on-board fabrication is still restricted in its precision. Therefore, misalignment may occur during bonding and cause damage to the passivation layer 13. Even worse, the force used in drawing the conducting line 15 along in the direction 18 may give rise to peeling and worsens the yield loss.
However, another bonding pad structure has been proposed whereby the width of the overhang region 14 is increased so as to enhance the adhesion between the conducting pad 12 and the passivation layer 13, but the tradeoff and hence the drawback is that layout area is large.
For the foregoing reason, there is a need for a novel bonding pad structure that can withstand peeling while the bonding procedure is performed and also consume less layout area.